Low supply voltage sub-bandgap reference circuit

ABSTRACT

A sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The circuit generates a negative temperature coefficient signal V be  and an oppositely tracking (positive temperature coefficient) ΔV be , and takes the average of two signals related to ΔV be -V be  to yield a temperature-compensated voltage of one-half the bandgap voltage of silicon. The circuit features an unequal area current mirror feeding the diodes and resistors used to generate the ΔV be -V be  signals using low supply voltages (less than 1.5 volts). A standard CMOS implementation provides low power consumption at a supply voltage of only 1 volt with a good temperature coefficient. The averaging circuit may be implemented by a continuous time divider or by using switched capacitor techniques. The loop amplifier used in the ΔV be -V be  circuitry operates with low headroom in part due to a n-well biasing scheme that lowers the effective threshold voltage of the p-channel FETs used in the loop amplifier.

This is a divisional of application Ser. No. 09/441,629 filed on Nov. 16, 1999, now U.S. Pat. No. 6,147,548, which is a divisional of application Ser. No. 08/926,649 filed on Sep. 10, 1997, now U.S. Pat. No. 6,052,020.

BACKGROUND

The invention relates generally to circuits and devices that produce a precise and stable DC signal, and more specifically, to temperature compensated bandgap reference circuits.

Virtually all systems that manipulate analog, digital or mixed signals, such as analog-to-digital and digital-to-analog converters, rely on at least one reference voltage as a starting point for all other operations in the system. Not only must a reference voltage be reproducible every time the circuit is powered up, the reference voltage must remain relatively unchanged with variations in fabrication process, operating temperature, and supply voltage.

A conventional technique for realizing a reference voltage uses the semiconductor bandgap reference circuit (also known as a bandgap reference). As explained in detail below, a bandgap reference relies on the predictable variation with temperature of the bandgap energy of the underlying semiconductor material. A practical way to obtain the behavior of the bandgap energy of a semiconductor material is to measure the “bandgap voltage” across a forward biased semiconductor P-N junction (diode) device. Although loosely referred to here as a diode, other devices such as transistors are also typically used to obtain the necessary P-N junction. For example, a conventional way to obtain a bandgap voltage is to diode-connect a bipolar junction transistor (BJT) such that the base to emitter voltage drop V_(be) is the voltage that exhibits bandgap behavior.

The term V_(be) historically originated with BJT-based bandgap reference circuits. In the remaining discussion, however, V_(be) is used to refer to any suitable diode-like element that exhibits a diode voltage drop.

FIG. 1 illustrates the extrapolated variation of V_(be) with temperature for two devices having the same emitter current but different current areas (and hence different current densities). If it were possible to generate a voltage that increased proportionally with temperature at the same rate at which V_(be) of a given transistor decreased, then the sum of the two voltages will be constant and equal to the bandgap voltage of approximately 1.205 volts, a physical constant. Therein lies the principle behind a bandgap reference.

A conventional bandgap reference 200 that attempts to implement the above principle is illustrated in FIG. 2. The circuit 200 essentially operates as a feedback control loop to maintain the two input nodes of amplifier 217 at approximately the same potential in the steady state. In so doing, the circuit 200 amplifies the difference ΔV_(be) between the voltages across diodes D₁ and D₂ which are operating at different values of current density due to their different cross-sectional areas. The difference ΔV_(be) will have a positive temperature coefficient, i.e., a rising slope as a function of temperature, as shown by the required compensation voltage line in FIG. 1, and will typically be several times smaller than the negative temperature coefficient V_(be). If the currents in the two unequal area diodes D₁ and D₂ are assumed to be the same in the steady state, and R₂ is set equal to R₃ for easy manipulation of the numbers, then the following equation may be derived by one skilled in the art:

V _(out) =ΔV _(be)(R ₂ /R ₁)+V _(be)

where ΔV_(be)=V_(D1)-V_(D2), V_(be)=V_(D1). The ratio R₁/R₂ is then selected as a gain factor to give V_(out) approximately equal to the zero Kelvin bandgap energy in electron volts of silicon, i.e., 1.205 volts. Thus, the bandgap principle introduced above is implemented with V_(out) being the temperature compensated reference voltage.

The bandgap reference 200 is an effective technique for obtaining a reference voltage of approximately 1.2 volts given a supply voltage of a few volts. The last 20 years, however, has seen a steady reduction in the supply voltage used for commercial electronic systems. Older systems typically operated based on a 5 volt supply, while many modem electronic systems that include very dense integrated circuits (ICs) now operate at approximately 3 volts. Electronic systems of the future will need to operate with even lower supply voltages of 1.5 volts or less. The lower headroom is required to maintain the reliability of future ICs by reducing their power densities. Lower supply voltages also reduce total power requirements thereby permitting extended operation time for portable electronics that use batteries. Furthermore, circuits that can operate with low supply voltages can be made compatible with the lower output of solar cells, thereby contributing to a cleaner environment.

The topology of bandgap reference 200 in FIG. 2, however, may require relatively high headroom in a supply voltage of a few volts or greater with respect to ground. Moreover, the reference output V_(out) lies typically between 1.2 and 1.3 volts, clearly unsuitable for systems having a 1.5 volts supply. Thus, to meet the challenge of such systems, there is a need to develop a low cost voltage reference circuit that can operate with supply voltages of 1.5 volts or less and that provides a reference output well below 1 volt.

SUMMARY

The invention is directed to a method for generating a reference signal. A first signal having a first value and a negative temperature coefficient is generated. A second signal having a second value and a positive temperature coefficient is generated. The first and second signals are sampled and stored on first and second capacitive elements, respectively. A low impedance path is created between the first and second capacitive elements to yield the reference signal across one of the capacitive elements.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” embodiment in this disclosure are not necessarily to the same embodiment, and they mean at least one.

FIG. 1 shows the known variation of V_(be) with temperature for two unequal area devices, and the required compensation to achieve the sum constant bandgap voltage.

FIG. 2 illustrates a prior art bandgap reference circuit.

FIG. 3 shows a low supply voltage sub-bandgap reference circuit according to an embodiment of the invention.

FIG. 4 depicts another embodiment of the sub-bandgap reference circuit of the invention.

FIG. 5 illustrates yet another embodiment of the invention's sub-bandgap reference circuit.

FIG. 6 illustrates an operational amplifier for use in an embodiment of the invention's sub-bandgap reference.

FIG. 7 is a schematic of a low-bias current generator cell for use in a current source block of another embodiment of the invention's sub-bandgap reference.

FIG. 8 is part of a power-on-reset block for kick starting the ΔV_(be)-ΔV_(be) circuit according to another embodiment of the invention.

FIG. 9 is a schematic of another embodiment of the invention's sub-bandgap reference including the power-on-reset and current source blocks.

DETAILED DESCRIPTION

The embodiments of the invention described in detail below are directed at a semiconductor circuit that generates a precise and stable reference voltage smaller than the semiconductor bandgap voltage and requiring low head room. The circuit achieves such a result by taking the average of a generated first signal having a negative temperature coefficient and a generated second signal having a positive temperature coefficient. The first and second signals are potentials that substantially track each other in opposite directions, their average therefore being temperature-compensated. In a preferred embodiment, the two signals are linearly separable components related to ΔV_(be) and V_(be) obtained using a technique similar to those used in conventional bandgap reference circuits.

The following detailed description of the various embodiments of the invention may often refer to specific numbers when describing the operation of various circuit elements. This is done only for purposes of explanation and not to define the actual scope of the invention. One skilled in the art will recognize that other numerical combinations may be readily available to accomplish substantially the same result, or to meet different performance requirements such as total power consumption, transient circuit response, and manufacturability.

FIG. 3 illustrates a sub-bandgap reference circuit 300 according to a preferred embodiment of the invention. The circuit 300 features a controlled current source 310 having an area-ratioed current mirror with three outputs feeding diode-like element D₂, diode-like element D₁, and resistor R₂, respectively. The voltage across D₁ is represented as V_(D1) or V_(be), the voltage across D₂ is V_(D2), and the difference V_(D1)-V_(D2)=ΔV or ΔV_(be). Diode-like element D₂ is coupled to the current source 310 in series with a resistor R₁. An averaging circuit 320 is coupled to R₂ and D₁ and provides an output voltage that is approximately the average of the voltages across R₂ and D₁.

The extensive analysis and description below will show that the voltages across R₂ and D₁ are related to the two opposite but equal-tracking (as a function of temperature) components ΔV_(be) and V_(be) conventionally seen in a bandgap reference circuit. Thus, the controlled source 310, amplifier A, and the network R₁-R₂-D₁-D₂ may be identified as the ΔV_(be)-V_(be) circuitry of this embodiment which generates signals related to V_(be) and ΔV_(be). The circuit 300 should be designed so that the temperature coefficient of the two signals precisely cancel each other when the two are equal. To accomplish this with minimum sensitivity to circuit parameters such as amplifier offsets, the circuit 300 features the use of a current mirror in controlled source 310 with non-equal current mirroring to increase the voltage term or signal related to ΔV_(be). It is desirable to make this term as large as possible to reduce the effects of errors (difference between design and actual values of circuit elements) and offsets in the amplifier A. Finally, the average of the ΔV_(be) and V_(be) related signals from R₂ and D₁ yields a temperature compensated voltage of approximately one-half the bandgap voltage of the semiconductor used for the diodes.

A key advantageous aspect of circuit 300 as well as other embodiments of the invention lies in the low headroom (low supply voltage) required by the circuit for operation. The low headroom is achieved by having at most one FET threshold voltage drop (VT) above nodes 323, 325 and 327. This allows the circuit 300 to operate with supply voltages of 1.5 volts or less.

Another advantageous aspect of the sub-bandgap circuit 300 in FIG. 3 is that the undesirable effects of different channel modulation on the different drain currents of the FETs in the current source 310 is reduced, because the operating drain-source voltages of the FETs are to be substantially equal by design. As explained more fully below, the voltages at nodes 327, 325 and 323 will be approximately equal, as required by the condition KΔV=V_(D1) needed to obtain a sub-bandgap temperature compensated output. By reducing such channel modulation in the FETs, the individual currents mI, nI, and I in the manufactured circuit will more precisely track the designed area ratio values of 1:n:m.

Circuit Operation of the First Embodiment

The circuit 300 includes an amplifier A (loop amplifier) whose output drives the current source 310 in response to inverting and non-inverting inputs received from D₁ and the line containing D₂. The amplifier A may be an operational amplifier that provides high open loop gain at low supply voltages of less than 1.5 v. An embodiment of the amplifier A is described below in connection with FIG. 6.

Turning to FIG. 3, in the steady state, the control loop that includes amplifier A drives the current source 310 such that the inverting and non-inverting inputs of amplifier A are approximately at the same potential, and the current I becomes constant. In that case, the respective currents through D₂, D₁ and R₂ are assigned to be I, nI, mI, (where n and m are positive numbers greater than one). Using the definitions for V_(D1), V_(D2), and ΔV above, the following mathematical relation may be written based on voltage loop equations from circuit 300:

IR ₁ +V _(D2) =V _(D1)

I=ΔV/R ₁ and

V ₃ =mIR ₂ =mΔV(R ₂ /R ₁)  (1)

where V₃ is the voltage at node 327. Thus, the inputs to the averaging circuit are mΔV(R₂/R₁) and V_(D1), the average of which yields a sub-bandgap temperature compensated voltage.

In order for a bandgap reference circuit to properly develop a temperature-compensated voltage, the difference between the design values and the actual values of the output voltage should be minimized. Even a 10 millivolt error may adversely affect the robustness of the output voltage in view of temperature as well as supply voltage variations. To achieve this accuracy, a more formal and mathematical explanation of the behavior of the sub-bandgap circuit now follows. The treatment may be used by one skilled in the art to further optimize the performance of the sub-bandgap circuit.

If the diode-like elements D₂ and D₁ have current area ratio A₂:A₁ (A₂>A₁), then the following expression may be written for V₃: $\begin{matrix} {V_{3} = {\frac{mkT}{q}{\ln \quad\left\lbrack {\frac{nI}{A_{1}} \cdot \frac{A_{2}}{I}} \right\rbrack}}} & (2) \end{matrix}$

where T is temperature in Kelvin, q is electronic charge, and k is the Boltzmann constant.

V_(D1) (hereinafter abbreviated as V_(D)) is a non-linear function of temperature and is given by the well-known equations $V_{D} = {\frac{kT}{q}\ln \quad \left( \frac{I}{I_{s}} \right)}$ I_(s) = cT^(η)^(−V_(g)q/kT)

where V_(g) is approximately=1.205 volts (bandgap voltage of silicon)

η is approximately=1.5 and

c is a proportionality constant related to the area of the diode.

We may assume that in the steady state, the currents I, nI, and mI will be relatively invariant with temperature as compared to the variation of a diode voltage drop V_(D1), such that ΔV and V₃ as given above in (1) and (2) are substantially linearly proportional to temperature.

Since V_(D1) decreases nonlinearly in value with temperature, while ΔV exhibits a substantially linear variation, there is only one value of V_(D1) and T for which $\begin{matrix} {{K\frac{{\Delta}\quad V}{T}} = \frac{V_{D1}}{T}} & (3) \end{matrix}$

where K is a constant gain factor (independent of temperature) to be selected such that (3) holds. The gain factor K is needed because the value of ΔV is typically several times smaller than V_(D1) for a given temperature and current. This linear versus non-linear aspect of the invention is an important consideration in realizing the optimum value of the sub-bandgap output.

Theoretically speaking, the condition (3) is necessary but may not be sufficient to generate a sub-bandgap voltage that is temperature invariant along the entire temperature range 0° C. to 100° C., because although the temperature coefficient of the ΔV term is fixed with respect to temperature, the temperature coefficient of V_(D1) is not.

Nevertheless, an approximate operation of circuit 300 to obtain the optimal resistor values and transistor dimensions may be explained by realizing that the circuit 300 contains a linearly separable voltage loop containing R₂. In other words, it can be shown that connecting R₂ to node 325 instead of common return (ground) allows a temperature-compensated output of approximately 1.2 volts (the bandgap voltage) to be generated at node 327. Therefore, circuit 300 for the sub-bandgap may be analyzed by evaluating the behavior of a modified circuit having resistor R₂ connected to node 325. For that scenario, an expression can be obtained for the voltage at node 327 with respect to ground as a function of temperature as follows.

Since the voltage V₃ at node 327 is equal to a diode drop V_(D1) across D₁ plus a voltage drop across resistor R₂, the following equation may be written:

V ₃ =mIR ₂ +V _(D1)  (4)

Differentiating (4) with respect to temperature and setting it equal to zero, and solving for the temperature at which dV₃/dT is equal to zero gives the optimal voltage V_(D1) at which the variation with temperature is the lowest over the entire temperature range. This is because the variation of V₃ with temperature is slightly non-linear such that the temperature T and voltage V_(D1) for which the slope of V₃ is equal to zero may be used to compute the optimal V₃ reference voltage. To obtain the desired expression for $\frac{V_{out}}{t},$

an expression may be written for current I based on the above equations as $\begin{matrix} {I = {{CT}^{\eta}^{\frac{q}{kT}{({V_{D1} - V_{g}})}}}} & (5) \end{matrix}$

Differentiating I in (5) with respect to temperature T gives $\begin{matrix} \begin{matrix} {{I_{c}} = \quad {{C_{\eta}T^{\eta - 1}^{\frac{q}{kT}{({V_{D1} - V_{g}})}}{T}} -}} \\ {\quad {{CT}^{\eta}^{\frac{q}{kT}{({V_{D1} - V_{g}})}}\frac{q}{kT}\left( {V_{D1} - V_{g}} \right)\frac{T}{T}}} \end{matrix} & (6) \end{matrix}$

The equation (6) can be simplified and rewritten by substituting equation (5) $\begin{matrix} {{I_{c}} = {{\frac{\eta}{T}I_{c}{T}} - {\frac{q}{kT}I_{c}\frac{V_{D1} - V_{g}}{T}{T}} + {\frac{q}{kT}I_{c}{V_{D1}}}}} & (7) \end{matrix}$

To simplify further analysis, we may assume that because the variation of I_(c) with temperature is relatively flat, $\begin{matrix} {\frac{I_{c}}{T} = \frac{I_{c}}{T}} & (8) \end{matrix}$

By substituting (8) into (7), we can rewrite (7) as $\begin{matrix} {\frac{V_{D1}}{T} = {{\frac{k}{q}\left( {1 - \eta} \right)} + \frac{V_{D1} - V_{g}}{T}}} & (9) \end{matrix}$

Now, differentiating (4) and substituting (8) gives $\begin{matrix} {\frac{V_{out}}{T} = {{R\frac{I_{c}}{T}} + {\frac{k}{q}\left( {1 - \eta} \right)} + \frac{V_{D1} - V_{g}}{T}}} & (11) \end{matrix}$

Using $\begin{matrix} {{{{{{{V_{out}}_{T = T_{0}} = V_{D1}}}_{T = T_{0}} + I}}_{T = T_{0}}R_{2}} = {V_{g} - {\frac{{kT}_{0}}{q}\left( {1 - \eta} \right)R_{2}}}} & (12) \end{matrix}$

which shows the bandgap condition V_(g)=KΔV+V_(D1) holds at absolute zero and at room temperature. Next, using $\begin{matrix} {{{{V_{D1}}_{T_{0}} = {V_{g} - {\frac{{kT}_{0}}{q}\left( {1 - \eta} \right)} - I}}}_{T_{0}}R_{2}} & (13) \end{matrix}$

and substituting (13) into (11) gives $\begin{matrix} {\frac{V_{3}}{T} = {\frac{k}{q}\left( {1 - {\eta \left( {1 - \frac{T}{T_{0}}} \right)}} \right)}} & (14) \end{matrix}$

integrating (14) with respect to temperature gives $\begin{matrix} {V_{3} = {V_{g} - {\frac{k}{q}{T\left( {1 - \eta} \right)}\left( {1 - {\ln \quad \left( \frac{T}{T_{0}} \right)}} \right)}}} & (15) \end{matrix}$

where T₀=296 Kelvin. Thus, equation (15) gives an expression of the temperature dependency of a full bandgap (1.2v) reference output. Using conventionally available numerical techniques, (15) was evaluated for a temperature range from 200-400 Kelvin. The results indicate that V₃ varies between 1.217 volts to 1.218 volts, using a value for η of 1.5, V_(g)=1.205, and kT₀/q=26 millivolts.

Given that a temperature-compensated full bandgap output V₃ has been determined for the modified circuit 300 having R₂ connected to node 325, the circuit designer can select particular numbers for the components of the original circuit 300 to yield the temperature-compensated sub-bandgap output by taking advantage of the linearly separable characteristics of the circuit 300.

To repeat, the voltage across R₂ is proportional to ΔV (and will thus exhibit a positive temperature coefficient), while the voltage V_(D1) will exhibit a substantially equal tracking but opposite negative temperature coefficient. However, because the temperature tracking of the two signals are not exactly equal (due to one being non-linear while the other is linear, as discussed above), there is only one temperature and diode voltage V_(D1) at which KΔV and V_(D1) have exactly the same but opposite temperature coefficients. That point is the temperature and voltage for which KΔV=V_(D1)=V_(g)/2 where V_(g) is the bandgap voltage of silicon. Thus, KΔV and V_(D1) will be equal to V₃/2 when resistor R₂ was connected to node 325, provided of course that the operating steady state conditions of the modified circuit 300 are unchanged for the sub-bandgap circuit 300, i.e., the currents through R₂, D₁, and D₂ remain substantially unchanged.

In a computer simulation performed on the circuit 300, a precise and stable sub-bandgap reference output of approximately 0.605 volts was indeed generated using a supply voltage of only 1 volt. The reference output exhibited a temperature coefficient of less than 80 parts per million (ppm) over a temperature range of approximately 0 to 150 degrees Celsius and less than 50 ppm over 0 to 50° C. The total power consumption of the sub-bandgap reference (including associated power-on-reset and current reference circuitry to be described below) was approximately 100 microWatts.

Description of Second Embodiment

FIGS. 4 and 5 illustrate other embodiments of the sub-bandgap reference of the invention as circuits 400 and 500. In circuit 400, bandgap circuitry represented by block 410 is configured to provide the diode voltage V_(D1) having a negative temperature coefficient and a voltage ΔV taken across R and having a positive temperature coefficient. The amplifier 417 has high open loop gain and drives controlled current source 427 such that in the steady state the voltage at the two input nodes of amplifier 417 are approximately equal. Gain block 435 is used to scale up ΔV such that at room temperature, V_(D1)=KΔV holds as a necessary condition for the existence of a sub-bandgap temperature-compensated output at V_(out).

The gain factor K and the necessary ΔV required to meet the bandgap condition may be obtained through several techniques. One such technique uses a switched capacitor implementation for the gain block 435. Gain block 435 should preferably provide substantially parasitic-free gain with low output impedance as compared to switch 421 and capacitive element C₂, as well as a high input impedance as compared to the value of R.

The averaging circuitry in FIG. 4 includes the switched capacitor network of C₁ and C₂ and the switches 421 and 425. By placing the necessary charge for each signal V_(D1) and ΔV in a capacitive element, and then shorting the capacitive elements together by a low impedance path, and average of the two signals can be obtained at V_(out).

An example of such a technique uses two capacitive elements C₁ and C₂ as shown in FIG. 4. In one embodiment, each of C₁ and C₂ may exhibit a capacitance on the order of a few tenths of a picoFarad, and are selected so as to reduce matching errors between the two elements (differences between design values and actual manufactured values), and to avoid sensitivity to capacitive and inductive parasitic effects present in the rest of the circuit. In the embodiment of FIG. 4, V_(D1) and ΔV are sampled almost simultaneously and corresponding charges Q₁=C₁V_(D1) and Q₂=C₂KΔV are placed in their respective capacitive elements via switches 425 and 421 in response to a control signal having phase φ₂. Next, a path having the lowest possible impedance between C₁ and C₂ is created by switch 423 in response to a control signal having phase φ₂. By effectively shorting C₁ and C₂, a new capacitive element is created with

Q=(C ₁ +C ₂)V

where V is the voltage across the now shorted capacitive elements C₁ and C₂. Substituting Q₁+Q₂ for Q and solving for V gives $\begin{matrix} {V = {\left( {Q_{1} + Q_{2}} \right)/\left( {C_{1} + C_{2}} \right)}} \\ {= {\left( {{C_{1}V_{1}} + {C_{2}\quad {K\Delta}\quad V}} \right)/\left( {C_{1} + C_{2}} \right)}} \\ {= {\left( {V_{D1} + {K_{c}{K\Delta}\quad V}} \right)/\left( {1 + K_{c}} \right)}} \end{matrix}$

where K_(c) is the ratio C₂/C₁. If C₁ is set equal to C₂, then the above equation gives

V=(V _(D1) +KΔV)/2

i.e., the voltage across the shorted capacitive elements C₁ and C₂ is the average of V_(D2) and KΔV, the desired sub-bandgap output. The voltage V is then sampled by sample-and-hold 431 in response to a control signal having phase φ₃ as shown in FIG. 4.

The three control signals are normally periodic and have non-overlapping phases φ₁, φ₂ and φ₃. The details of the control signals, namely the pulse amplitude and width, and the separation between successive signals as well as their frequency, are functions of the capacitance values for C₁ and C₂, the voltages across D₁ and D₂, the switching speed and impedance of the switches 425, 421, and 423, as well as the relevant characteristics of sample-and-hold 431, as will be apparent to one skilled in the art.

The averaging circuitry of the embodiment in FIG. 4 includes all circuitry outside the bandgap block 410, including switches 421, 425, and 423, as well as capacitive elements C₁ and C₂, and finally sample-and-hold 431. The averaging circuitry may also include the use of conventional techniques for generating the control signals φ₁, φ₂, and φ₃ having non-overlapping phase for controlling the switched capacitor network of C₁ and C₂ and the sample-and-hold. Other designs to accomplish essentially the same results as the averaging circuit in FIG. 4 using switched capacitors are possible, as shown in FIG. 5. In all cases, however, the averaging circuit must yield the sub-bandgap reference output signal V_(out) as an average of samples taken from the KΔV and V_(D1) signals.

Utilizing a switched capacitor design provides the advantages of lower manufacturing costs, easy implementation on a CMOS process, and lower power consumption. However, one disadvantage of using a switched capacitor design for gain block 435 is the introduction of switching noise. The switched capacitor network provides several advantages, such as very low power, excellent ratioing (leading to low matching errors in capacitance values), and digital control, in an otherwise relatively simple package comprising only two capacitors and a sample-and-hold amplifier.

However, a key disadvantage of the switched capacitor network is the difficulty of operation at supply voltages less than 1.5 volts, where switches 421, 423, and 425 may have particular difficulty in switching properly with such low headroom. Furthermore, current glitching due to the fast switching of FETs used in the switches may also be a problem, not only with respect to a source-drain current component but also with respect to a well component in a p-channel (n-well process) FET. To solve the above problems with the switched capacitor network, complex electronic circuitry may be needed that as a result complicates the design of a sub-bandgap reference circuit. Finally, the addition of the switched capacitor network may introduce undesirable parasitics to the sub-bandgap reference circuit.

Nevertheless, another embodiment of the sub-bandgap circuit using a slightly modified switched capacitor network for the averaging circuit is shown in FIG. 5. To obtain V_(D1) and KΔV, the circuit 500 features the ΔV_(be)-V_(be) circuitry 530 which also appears in circuit 300 of FIG. 3. The description and operation of the circuit 500 will be self-explanatory to one skilled in the art in light of the above discussion concerning FIGS. 3 and 4.

Circuit Components for Implementing the Embodiments of the Invention

The invention's sub-bandgap reference circuit employs an amplifier A for the control loop in all of the embodiments of the invention in FIGS. 3-5. The amplifier A should provide high gain with low offset over as wide of a common mode voltage range as possible. One possible implementation for the amplifier A is a folded cascode design. A folded cascode design is well-known for its capabilities in reducing noise at its output due to ripple on the power supply. The folded cascode design also provides increased common mode input range. However, the folded cascode design may not provide enough gain and stability at supply voltages close to 1 volt where the supply voltage can be as low as the threshold especially if the input common mode voltage is at {fraction (1/2+L )} the supply.

As an alternative to the folded cascode design, FIG. 6 is a schematic of an amplifier A that was satisfactorily simulated for operation at approximately 1 volt supply. The amplifier features a differential input stage wherein the input transistors I6 and I8 are p-channel FETs in a n-well fabrication process, and wherein the well of each FET receives a well-bias signal of approximately V_(T)/2 from p-channel FET I7. Carefully biasing the bulk (well) to substrate junction of a MOSFET near the turn on potential is used to reduce its effective threshold voltage. This is combined with well stacking or connecting the sources of the MOSFETs to the bulks to eliminate backgating or body effects, where possible, and to also reduce the threshold on stacked devices. Such a well biasing technique is also used in subcircuits of other embodiments of the invention described below to lower the effective threshold voltage of FETs.

For example, the effective threshold of a p-channel FET in a n-well process, for example, at the gate inputs of I6 and I8 of amplifier A in FIG. 6, may be reduced by slightly forward biasing the bulk (well) with respect to the source by approximately {fraction (3/10+L )} volt. This well biasing scheme reduces the headroom required for proper operation of the differential input stage of amplifier A.

The amplifier also features an output stage providing a large voltage gain through p-channel FET I5 that also receives a well-bias signal. This provides high open loop gain, which helps reduce the error in the value of the sub-bandgap output voltage. The well-bias signal PBODY is obtained from a different circuit, the low voltage current source (LVCS) or low-bias current generator cell of FIG. 7 described below. The well biasing scheme reduces the threshold voltage of a p-channel FET realized in a n-well. The n-well typically has an available terminal that can be set at any arbitrary bias. In FIG. 6, the bias comes from a resistor divider I14 and I15 connected to the source and drain of the diode-connected p-channel FET I7. The sum resistor value is selected such that the current through I7 is several times greater than the current through I14 and I15. FIG. 6, for example, shows the resistors as 250 kOhms each with I7 having W/L={fraction (10/2+L )} (in micrometers).

There may be potential problems with a well-bias design for the amplifier A in FIG. 6 if the design does not track the device threshold voltages of different production lots. By using a fixed divider across the reference FET I7, a threshold voltage tracking effect is achieved that makes the well-bias design of the amplifier A substantially independent of the fabrication process. Also, substrate contacting will help absorb the slight forward current (up to a few nanoAmps) in the well-to-substrate junction.

Techniques to further improve operation of the amplifier A at low supply voltages include the use of shorter channel and wider gate FETs to further reduce the threshold voltage of the FETs. To minimize the overall input offset voltage of the amplifier in FIG. 6, the dimensions of the various transistors in both stages of the amplifier can be adjusted so that an input offset presented by the output stage (including FET I5) is opposite in direction to the offset of the differential stage. Also, the relatively high gain of the output stage (including FET I5) helps reduce overall input offset by reducing the offset contribution of the differential stage to the overall offset.

Another part of the embodiment of the invention in FIG. 9 is the current source block I13 containing the LVCS of FIG. 7. The LVCS supplies biasing to various parts of the sub-bandgap reference circuit. The LVCS uses a MOSFET sub-threshold biasing scheme that generates a delta V_(T) across a resistor I19 in FIG. 7. This technique is effective in very low power or low voltage applications. The LVCS includes a conventional current loop bias generator using a Vittoz ΔV_(T) sub-threshold scheme. When operating in the sub-threshold region, an FET exhibits logarithmic drain current characteristics rather than the square law behavior in the normal operating region. The sub-threshold operating mode is based on diffused carriers (minority) instead of drift current (majority) which is the normal operating mode of an inverted surface FET. There are many desirable characteristics of an FET operated in this region, including maximum available gain and ability to use the FET as a reference.

The negative aspect of operating in the sub-threshold region is susceptibility to offset and noise as well as the difficulty of modeling FETs in this region. However, when the sub-threshold-biased MOSFET is used as a current source, most of these effects may be tolerated. In this region, the voltage drop across the source resistor I19 is a ΔV_(be) (ΔV_(T)) which reduces to a constant $\left( {{\frac{kT}{q}\ln \quad \frac{I_{1}}{A_{1}}} - {\frac{kT}{q}\ln \quad \frac{I_{2}}{A_{2}}}} \right) = {\frac{kT}{q}\ln \quad \left( \frac{I_{1}}{I_{2}} \right)}$

for areas A₁=A₂.

Well biasing is also used in the LVCS of FIG. 7 to reduce the supply operating voltage, obtained by resistors I7 and I8, and FET I1 having W/L={fraction (100/10)}.

Another component of the circuit in FIG. 9 is the Power On Reset (POR) circuit which is shown in FIG. 8. The POR is based on an RC circuit and threshold voltage of a p-channel. The POR circuit operates from the same low supply voltage as the rest of the sub-bandgap circuit is based on a Schmitt trigger design with a single feedback device, and a purposely low potential on a divider being a p-channel/n-channel ratio. The POR circuit includes some hysteresis with a crossing point at a low voltage, and generates output pulses POROUT and OUTBAR as shown in FIG. 8.

The goal of the POR circuit is to insure that sufficient supply voltage is present prior to enabling critical set-up voltages and enabling the LVCS and ΔV_(be)-V_(be) circuitry to be biased to the desired operating state. This is because the LVCS and the ΔV_(be)-V_(be) circuitry both employ closed control loops. Unless there is a start-up state which provides a current path to ground, the LVCS and ΔV_(be)-V_(be) circuitry may not be ensured a stable turn-on state. The advantage of this POR circuit is that it is effectively removed after the supply voltage has stabilized. Also, with the POR of FIG. 8, parasitic or undesired feedback loops are not formed which could result in malfunction of the sub-bandgap circuit. Also, after completion of the power on reset sequence described below, the POR circuit assumes an “off” condition which has negligible power dissipation.

The Power On Reset (POR) circuit of FIG. 8 sets the initial condition of any needed operating nodes in the sub-bandgap circuit of FIG. 9. For example, the POR circuit is used to kick start the ΔV_(be)-V_(be) circuitry which operates in closed loop fashion and may therefore benefit from such a start-up mode.

Finally, FIG. 9 illustrates a schematic of a complete sub-bandgap reference circuit according to another embodiment of the invention. The schematic includes all of the circuit blocks described above, including amplifiers (FIG. 6), LVCS (FIG. 7), POR (FIG. 8), ΔV_(be)-V_(be) circuitry 530, and averaging circuitry 920 which includes amplifiers I11, I12,l and I16 and is a variation of circuitry 320. The schematic includes the LVCS (I13) which provides current reference signals P_(out) (sink) and N_(out) (source) for biasing p-channel and n-channel FETs, respectively, and a threshold-reducing well-bias signal PBODY for a p-channel FET. The schematic also includes the POR (I14) that provides a pulse in response to detecting a rising voltage at the supply node Vcc. Several amplifiers I10, I11, I12, and I16 are used, which may be amplifier A described earlier and illustrated in FIG. 6, including the control loop amplifier I10, and buffer amplifiers I11, I12, and I16. The schematic also includes exemplary dimensions for the FETs I1, I2, I0 in the unequal area current mirror of current source 310 having the ratio 1:2:8.5, respectively. When the circuit of FIG. 9 is first powered up, the POR resets nodes in the LVCS to the proper potential. Once the supply has stabilized, the LVCS is then enabled which in turn biases the amplifiers. Thereafter, the ΔV_(be) and V_(be) are generated by circuitry 530 and averaged by circuitry 920 as described earlier to yield a buffered sub-bandgap reference voltage V_(OUT).

The embodiments of the sub-bandgap reference described above for exemplary purposes are, of course, subject to other variations in structure and implementation. In general, the design should have low currents so that lower power is consumed, although a trade off may need to be made with lower noise immunity and slower response. Also, lower currents reduce errors due to second and higher order effects present in the generation of KΔV and V_(D1). The lower currents also yield lower current matching errors in the various current mirrors used in the overall design by lowering drain potential differences and resistive drops. Also, in all of the embodiments of the invention described above, MOSFETs are used to illustrate embodiments of the invention which may be built using a standard sub-micron CMOS fabrication processes. Other types of transistors, however, are possible and within the grasp of one skilled in the art of analog circuit design, and may be built on fabrication processes other than standard CMOS.

Therefore, the scope of the invention should be determined not by the embodiments illustrated but by the appended claims and their legal equivalents. 

What is claimed is:
 1. A circuit comprising: a current source having first and second transistors that, as connected, can support different drain-source voltages and provide respective outputs; first and second diode elements coupled to said respective outputs of the current source at one end and to a common node at another end, the diode elements defining first and second diode voltages, respectively; a resistive element coupled to the common node at one end and being fed by a further output of the current source at another end; and an amplifier having an output coupled to control the current source in response to a signal at a first input coupled to the first diode element and a signal at a second input coupled to the second diode element.
 2. A circuit as in claim 1 wherein the current source comprises a current mirror feeding the first diode element, the second diode element, and the resistive element.
 3. A circuit as in claim 1 wherein the amplifier has a differential input stage receiving a well-bias signal to lower the threshold voltage of the differential input stage.
 4. The circuit as in claim 1 wherein the current source feeds the second diode element, the first diode element, and the resistive element with currents having the approximate relative ratio of 1:n:m, respectively.
 5. The circuit as in claim 1 wherein the first and second diode elements are made of silicon and the controlled current source draws its current from a supply node that receives approximately 1.5 Volts or less.
 6. A circuit as in claim 1 wherein the diode elements are diode-connected MOSFETs.
 7. A circuit as in claim 1 wherein the current source includes a plurality of p-channel MOSFETs for-respectively feeding the second diode element, the first diode element, and the resistive element, from a positive power supply node, the MOSFETs having their respective gates being coupled to the amplifier output.
 8. A circuit comprising: ΔV_(be)-V_(be) circuitry configured to provide a first signal having a negative temperature coefficient and a second signal having a positive temperature coefficient, the ΔV_(be)-V_(be) circuitry includes a current mirror, first and second diode elements, and a resistive element, the first signal derived from a voltage of the first diode element and the second signal derived from a voltage across the resistive element, the current mirror causing separate and directly proportional currents through the first and second diode elements and the resistive element, the ΔV_(be)-V_(be) circuitry further includes an amplifier that controls the current mirror in response to the voltages across the first and second diode elements.
 9. A circuit as in claim 8 further comprising power on reset circuitry that generates a reset pulse in response to detecting a rising voltage on a supply line for setting an initial condition of said ΔV_(be)-V_(be) circuitry.
 10. A method comprising: generating, via first, second, and third transistors, separate and proportional currents through first and second diode elements and a resistive element, respectively, the first and second diode elements and the resistive element being coupled to a common node; controlling the currents through the first and second elements and the resistive element based upon a difference between voltages across the first and second diode elements; and providing an output voltage proportional to a voltage across the resistive element. 